1. Field of the Invention
The present invention relates to a pipe latch circuit for increasing data output speed, a semiconductor memory device with the pipe latch circuit and data output operation method of the same that are capable of increasing data output speed by reducing an output path of pre-fetch data delivered at GIO lines and thus reducing the change of voltage level of the pre-fetch data.
2. Discussion of Related Art
In general, a data input/output of a synchronous semiconductor memory device is operated in synchronism with an internal clock signal generated on the basis of an external signal. This synchronous semiconductor memory device includes an SDR (Single Data Rate) SDRAM (Synchronous Dynamic Random Memory), a DDR (Double Data Rate) SDRAM and a DDR2 SDRAM, etc. The DDR2 SDRAM of the devices generally uses a 4 bit pre-fetch scheme. The 4 bit pre-fetch scheme is the method that, in the event that a READ command is once generated inside of a semiconductor memory device, 4 bit data are outputted in parallel from a memory cell array and then the 4 bit data are outputted in serial at an external device through one data input/output pin during 2 clock cycles.
As described above, because multi-bit data are outputted at an external device through one data input/output pin in a multi-bit pre-fetch type of a semiconductor memory device, parallel data outputted from a memory cell array have to be inverted into serial data. Therefore, the multi-bit pre-fetch type of a semiconductor memory device includes a pipe latch circuit for inverting parallel data read from the memory cell array into serial data.
FIG. 1 is a block diagram of conventional pipe latch circuit.
Referred to FIG. 1, the pipe latch circuit 10 includes a pipe input unit 20, a register 30, a first selection unit 40, a second selection unit 50 and a pipe output unit 60.
The pipe input unit 20 includes a plurality of pipe input circuits 21 through 24. The pipe input circuits 21 through 24 output pre-fetch data (EVD0, 0DD0, EVD1, 0DD1) received through GIO (Global Input and Output) lines GIOL0 through GIOL3 at the register 30 in response to an input control signal PPIN. The register 30 includes a plurality of latch circuits 31 through 34. The latch circuits 31 through 34 latch the pre-fetched data (EVD0, 0DD0, EVD1, 0DD1) respectively received from the input circuits 21 through 24, and then respectively outputs the latched data LATD0 through LATD3. The first selection unit 40 includes a plurality of selection circuits 41 through 44. The selection circuit 41 selects one of the latched data LATD0 and LATD1 in response to a selection control signal SOSEB0, and then outputs the selected data PRERD0. The selection circuit 42 selects one of the latched data LATD0 and LATD1 in response to a selection control signal SOSEB0, and then outputs the selected data PREFD0. The selection circuit 43 selects one of the latched data LATD2 and LATD3 in response to a selection control signal SOSEB0, and then outputs the selected data PRERD1. The selection circuit 44 selects one of the latched data LATD2 and LATD3 in response to a selection control signal SOSEB0, and then outputs the selected data PRFRD1.
On the other hand, the second selection unit 50 includes a plurality of selection circuits 51 and 52. The selection circuit 51 selects one of the selected data PRERD0 and PRERD1 in response to a selection control signal S0SEBR, and then outputs the selected data PRD0. The selection circuit 52 selects one of the selected data PREFD0 and PREFD1 in response to a selection control signal S0SEBF, and then outputs the selected data PFD0.
The pipe output unit 60 includes a plurality of pipe output circuits 61 and 62. The pipe output circuit 61 receives the selected data PRD0 from the selection circuit 51 in response to an output control signal POUTR, and then outputs the pipe output data RD0. The pipe output circuit 62 receives the selected data PFD0 from the selection circuit 52 in response to an output control signal POUTF, and then outputs the pipe output data FD0.
As mentioned above in detail, the pre-fetched data (EVD0, 0DD0, EVD1, 0DD1) have to be via 5 terminal devices (namely, the pipe input unit 20, the register 30, the first selection unit 40, the second selection unit 50 and the pipe output unit 60) in order to be outputted as the pipe output data RD0 and FD0 by the pipe latch circuit 10.
Meanwhile, because operation speed of recent semiconductor devices is getting faster and faster, demands on semiconductor memory devices for a high speed operation are increased more and more. However, the structure of the pipe latch circuit 10 including the 5 terminal devices is the restrictive factor on operation speed of a semiconductor memory device.
Additionally, in the pipe latch circuit 10, the latched data LATD0 through LATD3 may be varied (for example, may be reduced) while the latched data LATD0 through LATD3 are outputted via the first and second selection unit 40 and 50. This is the reason that input terminals of the second selection unit 50 are directly connected to output terminals of the first selection unit 40. The following is a detailed description with reference to the voltage variation.
The first and second selection unit 40 and 50 respectively select any one of input signals received through their input terminals in response to a selection control signal, and then output the selected signal itself at their input terminals. That is, the first and second selection unit 40 and 50 do not activate the input signals. Thus, the voltage value of the latched data LATD0 through LATD3 may be varied (for example, be reduced) by parasitic capacitance of the first and second selection unit 40 and 50 while the latched data LATD0 through LATD3 is outputted via the first and second selection unit 40 and 50.
For example, the voltage value of the selected data PRD0 and PFD0 inputted at the first selection unit 50 may be smaller than one of the latched data LATD0 through LATD3 inputted at the first selection unit 40. In this way, the pipe output unit 60 may output the error of the pipe output data RD0 and FD0 when the voltage value of the latched data LATD0 through LATD3 inputted at the first selection unit 40 is different from one of the selected data PRD0 through PFD0 outputted from the second selection unit 50.